Proceedings of the 32nd conference on Winter simulation
Capacity Optimization Planning System (Caps)
Interfaces
A discrete event simulation model simplification technique
WSC '05 Proceedings of the 37th conference on Winter simulation
Modeling semiconductor tools for small lotsize FAB simulations
Proceedings of the 38th conference on Winter simulation
Improved simple simulation models for semiconductor wafer factories
Proceedings of the 39th conference on Winter simulation: 40 years! The best is yet to come
Computers and Industrial Engineering
Winter Simulation Conference
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Linear and affine (Ax + B) models are commonly used to model equipment throughput in semiconductor wafer fabricator simulations. We endeavor to assess the quality of such models for the prohibitively expensive clustered photolithography scanner. The simulations demonstrate that such models are of varying quality. They can exhibit significant deviation from the system behavior when the simulation parameters, such as product mix and wafers per lot, change from those used to create the models. The error in throughput can range from about 4% to 60% as the number of wafers per lot varies from 24 to 1. These errors are of particular relevance for studies that consider a change to small lot sizes and high mix, as is predicted in the 450 mm era.