Pep8CPU: a programmable simulator for a central processing unit

  • Authors:
  • J. Stanley Warford;Ryan Okelberry

  • Affiliations:
  • Pepperdine University, Malibu, CA;Novell, Provo, UT

  • Venue:
  • Proceedings of the 38th SIGCSE technical symposium on Computer science education
  • Year:
  • 2007

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Abstract

This paper presents a software simulator for a central processing unit. The simulator features two modes of operation. In the first mode, students enter individual control signals for the multiplexers, function controls for the ALU, memory read/write controls, register addresses, and clock pulses for the registers required for a single CPU cycle via a graphical user interface. In the second mode, students write a control sequence in a text window for the cycles necessary to implement a single instruction set architecture (ISA) instruction. The simulator parses the sequence and allows students to single step through its execution showing the color-coded data flow through the CPU. The paper concludes with a description of the use of the software in the Computer Organization course and its availability for download on the Internet.