Three-valued automated reasoning on analog properties

  • Authors:
  • Raffaella Gentilini;Klaus Schneider;Alexander Dreyer

  • Affiliations:
  • University of Kaiserslautern, Kaiserslautern, UNK, Germany;University of Kaiserslautern, Kaiserslautern, UNK, Germany;Fraunhofer Inst. for Industrial Mathematics, Kaiserslautern, UNK, Germany

  • Venue:
  • Proceedings of the 17th ACM Great Lakes symposium on VLSI
  • Year:
  • 2007

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Abstract

We deal with the problem of designing suitable languages for the modeling and the automatic verification of properties over analog circuits. To this purpose, we suitably enrich classical temporal logics with basic formul\ae allowing to model arbitrary functions relating analog variables. We show how to automatically check the resulting CTLf formulæ on analog circuits. In particular, we rely on interval arithmetic methods and we extend to the analog context a number of techniques for the abstraction and the verification of digital systems, based on three-valued temporal logics.