The J-machine multicomputer: an architectural evaluation
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Designing interconnection networks for multi-level packaging
Proceedings of the 1993 ACM/IEEE conference on Supercomputing
Benefits of Processor Clustering in Designing Large Parallel Systems: When and How?
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
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A general framework for architectural design of large hierarchical multiprocessor systems under rapidly changing packaging, processor, and interconnection technologies is presented. In recent years processor boards with larger area (A) and greater pinouts are becoming feasible. Board interconnection technology has advanced from peripheral connections O(\sqrt A ) to elastomeric surface connections 0(A). As processor and interconnection technology grows, there is a varying demand on the interconnection network of the system. The proposed framework is capable of taking into account all these changes in technologies and, depending on a given set of technological parameters, derive the most optimum topology. The framework is illustrated by considering the design problem of the currently popular class of k-ary n-cube cluster-c scalable architectures.