SNAIL: A Multiprocessor Based on the Simple Serial Synchronized Multistage Interconnection Network Architecture

Authors:
Masashi Sasahara;Jun Terada;Luo Zhou;Kalidou Gaye;Jun-ichi Yamato;Satoshi Ogura;Hideharu Amano
Affiliations:
Keio University, Japan;Keio University, Japan;Keio University, Japan;Keio University, Japan;Keio University, Japan;Keio University, Japan;Keio University, Japan
Venue:
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
Year:
1994

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Abstract

Simple Serial Synchronized (SSS) Multistage Interconnection Network (MIN) is a novel MIN architecture for connecting processors and memory modules in multiprocessors. Synchronized bit-serial communication simplifies the structure/control, and also solves the pin-limitation problem. Here, design, implementation, and evaluation of a multiprocessor prototype called SNAIL with the SSS-MIN are presented. The heart of SNAIL is the prototype 1 /mu CMOS SSS-MIN gate array chip which exchanges packets from 16 inputs with 50MHz clock. The message combining is implemented only with 20% increases of the hardware. From the empirical evaluation with some application programs, it appears that the latency and synchronization overhead of the SSSMIN are tolerable, and the bandwidth of the SSS-MIN is sufficient. Although the performance improvement with the bit serial message combine is not so large (1%) when instructions are stored in the local memory, it becomes up to 400% when instructions are stored in the shared memory.