The performance of SNAIL-2 (a SSS-MIN connected multiprocessor with cache coherent mechanism)

Authors:
Takashi Midorikawa;Daisuke Shiraishi;Masayoshi Shigeno;Yasuki Tanabe;Toshihiro Hanawa;Hideharu Amano
Affiliations:
Department of Information and Computer Science, Amano Lab, Keio University, 3-14-1 Hiyoshi, Kohoku-ku, Yokohama 223-8522, Japan;Department of Information and Computer Science, Amano Lab, Keio University, 3-14-1 Hiyoshi, Kohoku-ku, Yokohama 223-8522, Japan;Department of Information and Computer Science, Amano Lab, Keio University, 3-14-1 Hiyoshi, Kohoku-ku, Yokohama 223-8522, Japan;Department of Information and Computer Science, Amano Lab, Keio University, 3-14-1 Hiyoshi, Kohoku-ku, Yokohama 223-8522, Japan;Department of Information Technology, Tokyo University of Technology, Tokyo, Japan;Department of Information and Computer Science, Amano Lab, Keio University, 3-14-1 Hiyoshi, Kohoku-ku, Yokohama 223-8522, Japan
Venue:
Parallel Computing
Year:
2005

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Abstract

Two component architectures for MIN-connected multiprocessors: PBSF (the piled banyan switching fabrics) and MINC (MIN with cache consistency mechanism) are evaluated with a real machine SNAIL-2 and an instruction level simulator. The PBSF is a high bandwidth MIN with three dimensional structure, and the MINC is a mechanism for controlling the consistency of private cache modules located between processors and the MIN. Empirical implementation and simulation results show that the performance improvement of cache controlled by the MINC is significant, and throughput of the PBSF is sufficient if the cache is provided.