Design of sequential circuits by quantum-dot cellular automata

Authors:
J. Huang;M. Momenzadeh;F. Lombardi
Affiliations:
Department of Electrical and Computer Engineering, Northeastern University, USA;Department of Electrical and Computer Engineering, Northeastern University, USA;Department of Electrical and Computer Engineering, Northeastern University, USA
Venue:
Microelectronics Journal
Year:
2007

Citing 4
Cited 7

Logic design theory

Logic design theory
Exploring and exploiting wire-level pipelining in emerging technologies

ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Introduction to Algorithms

Introduction to Algorithms
Defect Characterization and Tolerance of QCA Sequential Devices and Circuits

DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Arithmetic Design on Quantum-Dot Cellular Automata Nanotechnology

SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Applying inherent capabilities of quantum-dot cellular automata to design: D flip-flop case study

Journal of Systems Architecture: the EUROMICRO Journal
Design and simulation of sequential circuits in quantum-dot cellular automata: Falling edge-triggered flip-flop and counter study

Microelectronics Journal
Design of a Goldschmidt iterative divider for quantum-dot cellular automata

NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
Novel RAM cell designs based on inherent capabilities of quantum-dot cellular automata

Microelectronics Journal
Layout design of manufacturable quantum-dot cellular automata

Microelectronics Journal
A module-level three-stage approach to the evolutionary design of sequential logic circuits

Genetic Programming and Evolvable Machines

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper proposes a detailed design analysis of sequential circuits for quantum-dot cellular automata (QCA). This analysis encompasses flip-flop (FF) devices as well as circuits. Initially, a novel RS-type FF amenable to a QCA implementation is proposed. This FF extends a previous threshold-based configuration to QCA by taking into account the timing issues associated with the adiabatic switching of this technology. The characterization of a D-type FF as a device consisting of an embedded wire is also presented. Unique timing constraints in QCA sequential logic design are identified and investigated. An algorithm for assigning appropriate clocking zones to a QCA sequential circuit is proposed. A technique referred to as stretching is used in the algorithm to ensure timing and delay matching. This algorithm relies on a topological sorting and enumeration step to consistently traversing only once the edges of the graph representation of the QCA sequential circuit. Examples of QCA sequential circuits are provided.