Computer organization & design: the hardware/software interface
Computer organization & design: the hardware/software interface
The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Computer Organization
Splitting the Data Cache: A Survey
IEEE Concurrency
Itanium 2 Processor Microarchitecture
IEEE Micro
mlcache: A Flexible Multi-Lateral Cache Simulator
MASCOTS '98 Proceedings of the 6th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems
Computer Architecture: A Quantitative Approach
Computer Architecture: A Quantitative Approach
Computer Organization and Architecture: Designing for Performance (7th Edition)
Computer Organization and Architecture: Designing for Performance (7th Edition)
A lab course of computer organization
WCAE '02 Proceedings of the 2002 workshop on Computer architecture education: Held in conjunction with the 29th International Symposium on Computer Architecture
Understanding cache hierarchy interactions with a program-driven simulator
WCAE '07 Proceedings of the 2007 workshop on Computer architecture education
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Cache memories are the most ubiquitous mechanisms devoted to hide memory latencies in current microprocessors. Due to this importance, they are a core topic in computer architecture curricula, both in graduate and undergraduate courses. As a consequence, traditional literature and current educational proposals devote important efforts to this topic. In this context, exercises dealing with simple algorithms, also known as code-based exercises, have a good acceptance among instructors because they permit students to realize how the accesses generated by the programs affect the cache's state. From about one decade ago, simulators have been extensively employed as a valuable pedagogical tool as they enable students to visualize how computer units work and interact each other. Unfortunately, there is no simple simulator allowing to perform code-based exercises for cache memories. Hence, students perform these exercises by means of the classic "paper and pencil" methodology. In this paper we introduce Spim-cache, a simple execution-driven cache simulator to carry out such experiments, intended to use in undergraduate courses. The tool allows, in an intuitive and easy way, to select a given cache organization and run step-by-step the code proposed while visualizing dynamic changes in the cache's state.