A VLIW architecture for a trace Scheduling Compiler
IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
WinDLX and MIPSim Pipeline Simulators for Teaching Computer Architecture
ECBS '96 Proceedings of the IEEE Symposium and Workshop on Engineering of Computer Based Systems
Very Long Instruction Word architectures and the ELI-512
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Automatic Architectural Synthesis of VLIW and EPIC Processors
Proceedings of the 12th international symposium on System synthesis
Teaching basics of instruction pipelining with HDLDLX
WCAE '04 Proceedings of the 2004 workshop on Computer architecture education: held in conjunction with the 31st International Symposium on Computer Architecture
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VLIW-DLX is graphical simulator of simple VLIW processor. It is targeted to be used in undergraduate computer architecture courses. VLIW-DLX uses similar GUI to well-known WinDLX simulator and its ISA uses scalar DLX instructions as the building blocks. Simulator is implemented in Java and allows future modifications of the architecture including instruction set expansion. Paper discusses choices made in developing VLIW-DLX and its intended educational use.