Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
WinDLX and MIPSim Pipeline Simulators for Teaching Computer Architecture
ECBS '96 Proceedings of the IEEE Symposium and Workshop on Engineering of Computer Based Systems
An interactive, visual simulator for the DLX pipeline
WCAE-3 '97 Proceedings of the 1997 workshop on Computer architecture education
MipsIt: a simulation and development environment using animation for computer architecture education
WCAE '02 Proceedings of the 2002 workshop on Computer architecture education: Held in conjunction with the 29th International Symposium on Computer Architecture
VLIW-DLX simulator for educational purposes
WCAE '07 Proceedings of the 2007 workshop on Computer architecture education
A full system x86 simulator for teaching computer organization
Proceedings of the 42nd ACM technical symposium on Computer science education
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HDLDLX is a graphically described VHDL model of 5-stage integer pipeline of well known DLX processor. It can be used as a platform explaining logic-level implementation of pipelined processor as a complement to SW functional simulators. Students can interact with model by implementing hazard resolution logic or modifying the pipeline structure. Even though that the model is internally represented in VHDL, the previous knowledge of this language is not required. HDLDLX can be used in conjunction with HDL Designer and Modelsim tools from Mentor Graphics corporation. Article also discusses pros and cons of using commercial EDA tools in undergraduate computer architecture course.