Toward Automatic Synthesis of Schedulable Real-Time Controllers

  • Authors:

  • Minsoo Ryu;Seongsoo Hong

  • Affiliations:

  • School of Electrical Engineering, Seoul National University, San 56-1 Shinlim-Dong, Kwanak-Ku, Seoul, 151-742, South Korea;School of Electrical Engineering, Seoul National University, San 56-1 Shinlim-Dong, Kwanak-Ku, Seoul, 151-742, South Korea

  • Venue:
  • Integrated Computer-Aided Engineering
  • Year:
  • 1998

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Abstract

This paper presents an automatic approach to synthesizing schedulable timing constraints for real-time control systems. Given the performance specifications and schedulability constraints of a real-time control system, the approach derives task-level timing constraints which can guarantee these requirements. The control performance is specified in terms of control output responses such as steady state error, maximum over-shoot, settling time, and rise time, and the task-level timing constraints include task periods and deadlines. The approach consists of two components with a clean interface. The first component translates the performance specifications into a set of system-level timing constraints such as loop processing periods and input-to-output latency, via control theoretic modeling and optimization. The second then derives task-level timing constraints from the intermediate system-level timing constraints optimizing the system schedulability using the period calibration method (Gerber et al., 1995; Saksena et al., 1996; Kim et al., 1996). Our approach contributes to both the control and real-time areas: (1) it allows control engineers to take into consideration the effect of task scheduling at the early stage of system design; and (2) it makes it possible to streamline the design of real-time control systems, since timing constraints are derived in an automatic manner.