Modern Digital and Analog Communication Systems 3e Osece
Modern Digital and Analog Communication Systems 3e Osece
Low-power asynchronous viterbi decoder for wireless applications
Proceedings of the 2004 international symposium on Low power electronics and design
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
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This paper presents a 64-state, ½-rate asynchronous Viterbi decoder suitable for wireless and mobile applications. The decoder uses a novel dynamic Current Sensing Completion Detection (CSCD) technique and achieves significant power reduction while maintaining speed. The decoder, implemented in a 90 nm CMOS technology, occupies an area of 0.81 mm2 and operates at 378 Mb/s while consuming 45 mW: a 43% power delay product improvement when compared to its synchronous counterpart.