Modern Digital and Analog Communication Systems 3e Osece
Modern Digital and Analog Communication Systems 3e Osece
A Low-Power Self-Timed Viterbi Decoder
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
Error control coding in low-power wireless sensor networks: when is ECC energy-efficient?
EURASIP Journal on Wireless Communications and Networking
A low-power CSCD asynchronous viterbi decoder for wireless applications
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Design of a low-power embedded processor architecture using asynchronous function units
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
A low-power globally synchronous locally asynchronous FFT processor
HPCC'07 Proceedings of the Third international conference on High Performance Computing and Communications
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This paper describes the implementation of an asynchronous 64-state, 1/2-rate Viterbi decoder using an original architecture and design methodology. The decoder is intended for wireless communications applications, where bit rates over 100 Mb/s and minimum power consumption are sought. The choice of an asynchronous design was predicated by the power and speed advantages of such a methodology. Asynchronous designs are inherently data driven and are active only when doing useful work, enabling considerable savings in power and operating at the average speed of all components. The decoder, implemented in a 0.18 µm CMOS technology, occupies an area of 2 mm 2 and operates above 200 Mb/s while consuming 85 mW: a 55% power reduction when compared to state of the art synchronous design implemented in a 0.25 µm technology.