Computer organization and design (2nd ed.): the hardware/software interface
Computer organization and design (2nd ed.): the hardware/software interface
A parallel embedded-processor architecture for ATM reassembly
IEEE/ACM Transactions on Networking (TON)
Wcdma for Umts
Multiprocessor DSP Scheduling in System-on-a-chip Architectures
ECRTS '02 Proceedings of the 14th Euromicro Conference on Real-Time Systems
SoC Features for a Multi-Processor WCDMA Base-station Modem
IWSOC '04 Proceedings of the System-on-Chip for Real-Time Applications, 4th IEEE International Workshop
A new single-ended SRAM cell with write-assist
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Advanced signal processing for voice and data in wired or wireless environments can require massive computational power. Due to the complexity and continuing evolution of such systems, it is desirable to maintain as much software controllability in the field as possible. Time to market can also be improved by reducing the amount of hardware design. This paper describes an architecture based on clusters of embedded "workhorse" processors which can be dynamically harnessed in real time to support a wide range of computational tasks. Low-power processors and memory are important ingredients in such a highly parallel environment.