Opportunities and Limits of Remote Timing Attacks
ACM Transactions on Information and System Security (TISSEC)
Hardware trust implications of 3-D integration
WESS '10 Proceedings of the 5th Workshop on Embedded Systems Security
Side-channel analysis of cryptographic software via early-terminating multiplications
ICISC'09 Proceedings of the 12th international conference on Information security and cryptology
Hardware assistance for trustworthy systems through 3-D integration
Proceedings of the 26th Annual Computer Security Applications Conference
Caisson: a hardware description language for secure information flow
Proceedings of the 32nd ACM SIGPLAN conference on Programming language design and implementation
A qualitative security analysis of a new class of 3-d integrated crypto co-processors
Cryptography and Security
Inspection resistant memory: architectural support for security from physical examination
Proceedings of the 39th Annual International Symposium on Computer Architecture
Improvement of trace-driven I-Cache timing attack on the RSA algorithm
Journal of Systems and Software
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This installment of Crypto Corner looks at some specific new side channels that are enabled by the very sophisticated ingredients of modern microprocessor architectures.