Testing configurable LUT-based FPGA's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-line fault detection for bus-based field programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA and CPLD Architectures: A Tutorial
IEEE Design & Test
System-on-Chip Oriented Fault-Tolerant Sequential Systems Implementation Methodology
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
On-line Diagnosis and Reconfiguration of FPGA Systems
DELTA '02 Proceedings of the The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
Column-Based Precompiled Configuration Techniques for FPGA
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Online BIST and BIST-based diagnosis of FPGA logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Many techniques have been proposed in the technical literature for repairing FPGAs when affected by permanent faults. Almost all of these works exploit the dynamic reconfiguration capabilities of an FPGA where a subset of the available resources is used as spares for replacing the faulty ones. The choice of the best reconfiguration technique depends on both the required reliability and on the architecture of the chosen FPGA . This paper presents a survey of these techniques and explains how the architectural organization of the FPGA affects the choice of a reconfiguration strategy. Subsequently, a framework is proposed for these techniques by which a fair comparison among them can be assessed and evaluated with respect to reliability. A reliability evaluation is provided for different repair strategies. To provide a comparison between these techniques FPGAs of different size are taken into account. Also the relationship between the area overhead and the overall reliability has been investigated. Considerations about time to repair and feasibility of these techniques are provided. The ultimate goal of this paper is therefore to present a state-of-the-art repair techniques as applicable to FPGA and to establish their performance for reliability.