VHDL description of a synthetizable and reconfigurable real-time stereo vision processor

Authors:
Carlos Cuadrado;Aitzol Zuloaga;José L. Martín;Jesús Lázaro;Jaime Jiménez
Affiliations:
Dept. of Electronics and Telecommunications, University of the Basque Country, Bilbao, Spain;Dept. of Electronics and Telecommunications, University of the Basque Country, Bilbao, Spain;Dept. of Electronics and Telecommunications, University of the Basque Country, Bilbao, Spain;Dept. of Electronics and Telecommunications, University of the Basque Country, Bilbao, Spain;Dept. of Electronics and Telecommunications, University of the Basque Country, Bilbao, Spain
Venue:
ISPRA'05 Proceedings of the 4th WSEAS International Conference on Signal Processing, Robotics and Automation
Year:
2005

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Abstract

This paper describes a reconfigurable digital architecture to compute dense disparity maps at video-rate for stereo vision. The processor architecture is described in synthetizable VHDL and, by means of the reconfigurability, the hardware requirements are optimized for different image resolutions and matching scenarios. To have a configurable description of a stereo processor provides the entity to design hardware stereo matching systems, implementing by incremental design disparity consistence algorithms, multi-stereo correlations or multi-scale algorithms. The results of the hardware synthesis of this code have being implemented in several reconfigurable devices. We show the results of the synthesis and its implementation cost in logic elements and delays.