Performance Analysis of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
The Odd-Even Turn Model for Adaptive Routing
IEEE Transactions on Parallel and Distributed Systems
Advanced Computer Architecture: Parallelism,Scalability,Programmability
Advanced Computer Architecture: Parallelism,Scalability,Programmability
Advanced Multi-Microprocessor Bus Architectures
Advanced Multi-Microprocessor Bus Architectures
Limits on Interconnection Network Performance
IEEE Transactions on Parallel and Distributed Systems
Deadlock Avoidance for Switches Based on Wormhole Networks
ICPP '99 Proceedings of the 1999 International Conference on Parallel Processing
GOAL: a load-balanced adaptive routing algorithm for torus networks
Proceedings of the 30th annual international symposium on Computer architecture
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In this paper, we propose two hypercube-based, off-chip interconnect architectures, called 3D-interconnects, to communicate between processing elements and memory modules located on network linecards. Our main goal is to increase the throughput of the memory system since most currently deployed linecard designs reach their maximum transfer rate. Moreover, line rates are constantly increasing while at the same time more data and functionality are embedded in each packet. The 3D-interconnect architectures allow multiple packet processing elements on a linecard to access multiple memory modules. The novelty of the proposed interconnects is their application and implementation as off-chip interconnects on the linecard board. Our interconnects include multiple, highly efficient techniques to route, switch, and control packet flows in order to minimize congestion spots within the interconnects and packet loss. Performance results show that both 3D-interconnects, studied in this paper, achieve high throughput, low latency results surpassing other common interconnects currently deployed. Furthermore, the interconnects were able to sustain high traffic load while keeping low failure rates and high bandwidth utilization levels.