Deadlock Avoidance for Wormhole Based Switches
Euro-Par '00 Proceedings from the 6th International Euro-Par Conference on Parallel Processing
Modelling and simulation of off-chip communication architectures for high-speed packet processors
Journal of Systems and Software
High performance architectures for Chip-to-Chip Communications on Network Line Cards
Journal of High Speed Networks
Off-chip communication architectures for high throughput network processors
Computer Communications
Performance evaluation of wormhole routed network processor-memory interconnects
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
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We consider the use of wormhole routed networks as internal interconnects of switches. The interconnection of two wormhole networks that are free from deadlocks does not necessarily produce a deadlock free network. This is problematic when wormhole networks are used as switch-internal fabrics, because it severely restricts the possibilities for coupling the switches together. This paper presents a theory that can be effectively used to control this phenomenon caused by aggregated dependencies. We show that all aggregated dependencies can be removed from wormhole networks by careful inclusion of a limited number of virtual channels.