Performance evaluation of wormhole routed network processor-memory interconnects

  • Authors:
  • Taskin Kocak;Jacob Engel

  • Affiliations:
  • School of Electrical Engineering and Computer Science, University of Central Florida, Orlando, FL;School of Electrical Engineering and Computer Science, University of Central Florida, Orlando, FL

  • Venue:
  • IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
  • Year:
  • 2006

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Abstract

Network line cards are experiencing ever increasing line rates, random data bursts, and limited space. Hence, they are more vulnerable than other processormemory environments, to create data transfer bottlenecks and hot-spots. Solutions to the memory bandwidth bottleneck are limited by the area available on the line card and network processor I/O pins. As a result, we propose to explore more suitable off-chip interconnect and communication mechanisms that will replace the existing systems and that will provide extraordinary high throughput. We utilize our custom-designed, event-driven, interconnect simulator to evaluate the performance of wormhole routed packet-based off-chip k-ary n-cube interconnect architectures for line cards. Our performance results show that wormhole routed k-ary n-cube based interconnect topologies significantly outperform the existing line card interconnects and they are able to sustain higher traffic loads.