Temporal logic for real time systems
Temporal logic for real time systems
Specifying real-time properties with metric temporal logic
Real-Time Systems
The temporal logic of reactive and concurrent systems
The temporal logic of reactive and concurrent systems
Temporal verification of reactive systems: safety
Temporal verification of reactive systems: safety
A framework for object oriented hardware specification, verification, and synthesis
Proceedings of the 38th annual Design Automation Conference
Model Checking of Safety Properties
Formal Methods in System Design
Introduction to Algorithms
Another Look at LTL Model Checking
Formal Methods in System Design
The Temporal Rover and the ATG Rover
Proceedings of the 7th International SPIN Workshop on SPIN Model Checking and Software Verification
Synthesizing Monitors for Safety Properties
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Examples of a Real-Time Temporal Logic Specification
The Analysis of Concurrent Systems
Quantitative Temporal Reasoning
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Expressibility results for linear-time and branching-time logics
Linear Time, Branching Time and Partial Order in Logics and Models for Concurrency, School/Workshop
Parametric Quantitative Temporal Reasoning
LICS '99 Proceedings of the 14th Annual IEEE Symposium on Logic in Computer Science
Real-time programming and asynchronous message passing
PODC '83 Proceedings of the second annual ACM symposium on Principles of distributed computing
Synthesizing Dynamic Programming Algorithms fromLinear Temporal Logic Formulae
Synthesizing Dynamic Programming Algorithms fromLinear Temporal Logic Formulae
An Overview of the Runtime Verification Tool Java PathExplorer
Formal Methods in System Design
LOLA: Runtime Monitoring of Synchronous Systems
TIME '05 Proceedings of the 12th International Symposium on Temporal Representation and Reasoning
Collecting Statistics Over Runtime Executions
Formal Methods in System Design
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
A mixed-signal verification kit for verification of analogue-digital circuits
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Simulation Based Verification using Temporally Attributed Boolean Logic
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
SFCS '89 Proceedings of the 30th Annual Symposium on Foundations of Computer Science
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We propose a specification logic called Temporally Attributed Boolean (TAB) Logic for Assertion Based Verification, which allows us to: (i) represent assertions succinctly, (ii) incorporate data-orientation and (iii) associate timing to design intentions. TAB Logic allows us to write specifications functionally linking system variables from different temporal contexts. We present examples to show the motivation for this logic especially in the context of high level modeling of complex real time systems. We formally define TAB Logic, formulate the problem of verification on a simulation trace and present efficient algorithms to check TAB assertions, both offline and online. We present results of application of TAB Logic for Instruction Semantics and Bus Transaction Verification of a bus integrated pipelined processor core implementation. We also employ TAB Logic to validate the Interrupt mode behavior of the processor core implementation. Further, we show the utility of TAB Logic in fault detection. Finally, we demonstrate the applicability of TAB Logic in the domain of simulation based verification of analog circuits like Operational Amplifiers and DC-DC Converters. We finally discuss the limitations of TAB logic and conclude.