An efficient FPGA implementation of principle component analysis based network intrusion detection system

Authors:
Abhishek Das;Sanchit Misra;Sumeet Joshi;Joseph Zambreno;Gokhan Memik;Alok Choudhary
Affiliations:
Northwestern University, Evanston IL;Northwestern University, Evanston IL;Indian Institute of Technology, Kharagpur, India;Iowa State University, Ames, IA;Northwestern University, Evanston IL;Northwestern University, Evanston IL
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
2008

Citing 8
Cited 1

A Fine-Grained Parallel Pipelined Karhunen-Loève Transform

IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Intrusion Detection Testing and Benchmarking Methodologies

IEEE-IWIA '03 Proceedings of the First IEEE International Workshop on Information Assurance (IWIA'03)
Time and area efficient pattern matching on FPGAs

FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Efficient packet classification for network intrusion detection using FPGA

Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Fast Regular Expression Matching Using FPGAs

FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Efficient Hardware Data Mining with the Apriori Algorithm on FPGAs

FCCM '05 Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A Framework for Rule Processing in Reconfigurable Network Systems

FCCM '05 Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Architecture for a Hardware-Based, TCP/IP Content-Processing System

IEEE Micro

Massively parallel acceleration of a document-similarity classifier to detect web attacks

Journal of Parallel and Distributed Computing

Quantified Score

Hi-index	0.00

Visualization

Abstract

Modern Network Intrsuion Detection Systems (NIDSs) use anomaly detection to capture malicious attacks. Since such connections are described by large set of dimensions, processing these huge amounts of network data becomes extremely slow. To solve this time-efficiency problem, statistical methods like Principal Component Analysis (PCA) can be used to reduce the dimensionality of the network data. In this paper, we design and implement an efficient FPGA architecture for Principal Component Analysis to be used in NIDSs. Moreover, using representative network intrusion traces, we show that our architecture correctly classifies attacks with detection rates exceeding 99.9% and false alarm rates as low as 1.95%. Our implementation on a Xilinx Virtex-II Pro FPGA platform provides a core throughput of up to 24.72 Gbps, clocking at a frequency of 96.56 MHz.