Numerical recipes in C (2nd ed.): the art of scientific computing
Numerical recipes in C (2nd ed.): the art of scientific computing
Neural Network-Based Face Detection
IEEE Transactions on Pattern Analysis and Machine Intelligence
The Transmogrifier-2: a 1 million gate rapid-prototyping system
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Detecting Faces in Images: A Survey
IEEE Transactions on Pattern Analysis and Machine Intelligence
Comparing Images Using the Hausdorff Distance
IEEE Transactions on Pattern Analysis and Machine Intelligence
Real-Time Face Detection on a Configurable Hardware System
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Rotation Invariant Neural Network-Based Face Detection
CVPR '98 Proceedings of the IEEE Computer Society Conference on Computer Vision and Pattern Recognition
Embedded Hardware Face Detection
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
An Efficient Approach to Custom Instruction Set Generation
RTCSA '05 Proceedings of the 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
AdaBoost-based face detection for embedded systems
Computer Vision and Image Understanding
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Over recent years automated face detection and recognition (FDR) have gained significant attention from the commercial and research sectors. This paper presents an embedded face detection solution aimed at addressing the real-time image processing requirements within a wide range of applications. As face detection is a computationally intensive task, an embedded solution would give rise to opportunities for discrete economical devices that could be applied and integrated into a vast majority of applications. This work focuses on the use of FPGAs as the embedded prototyping technology where the thread of execution is carried out on an embedded soft-core processor. Custom instructions have been utilized as a means of applying software/hardware partitioning through which the computational bottlenecks are moved to hardware. A speedup by a factor of 110 was achieved from employing custom instructions and software optimizations.