Reductions for monotone Boolean circuits

Authors:
Kazuo Iwama;Hiroki Morizumi;Jun Tarui
Affiliations:
Graduate School of Informatics, Kyoto University, Kyoto 606-8501, Japan;Graduate School of Informatics, Kyoto University, Kyoto 606-8501, Japan;Department of Information and Communication Engineering, University of Electro-Communications, Chofu, Tokyo 182-8585, Japan
Venue:
Theoretical Computer Science
Year:
2008

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Abstract

The large class, say NLOG, of Boolean functions, including 0-1 Sort and 0-1 Merge, have an upper bound of O(nlogn) for their monotone circuit size, i.e., they have circuits with O(nlogn) AND/OR gates of fan-in two. Suppose that we can use, besides such normal AND/OR gates, any number of more powerful ''F-gates'' which realize a monotone Boolean function F with r(=2) inputs and r^'(=1) outputs. Note that the cost of each AND/OR gate is one and we assume that the cost of each F-gate is r. Now we define: A Boolean function f in NLOG is said to be F-Easy if f can be constructed by a circuit with AND/OR/F gates whose total cost is o(nlogn). In this paper we show that 0-1 Merge is not F-Easy for an arbitrary monotone function F such that r^'@?r/logr.