On the negation-limited circuit complexity of merging
Discrete Applied Mathematics - Special issue: Special issue devoted to the fifth annual international computing and combinatories conference (COCOON'99) Tokyo, Japan 26-28 July 1999
On the minimum number of negations leading to super-polynomial savings
Information Processing Letters
Limiting negations in bounded-depth circuits: an extension of Markov's theorem
Information Processing Letters
Reductions for monotone Boolean circuits
Theoretical Computer Science
Linear-size log-depth negation-limited inverter for k-tonic binary sequences
Theoretical Computer Science
Limiting Negations in Formulas
ICALP '09 Proceedings of the 36th International Colloquium on Automata, Languages and Programming: Part I
Note: Limiting negations in non-deterministic circuits
Theoretical Computer Science
Linear-size log-depth negation-limited inverter for k-tonic binary sequences
TAMC'07 Proceedings of the 4th international conference on Theory and applications of models of computation
On the negation-limited circuit complexity of sorting and inverting k-tonic sequences
COCOON'06 Proceedings of the 12th annual international conference on Computing and Combinatorics
Reductions for monotone boolean circuits
MFCS'06 Proceedings of the 31st international conference on Mathematical Foundations of Computer Science
Negation-Limited complexity of parity and inverters
ISAAC'06 Proceedings of the 17th international conference on Algorithms and Computation
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A theorem of Markov precisely determines the number r of NEGATION gates necessary and sufficient to compute a system of boolean functions F. For a system of boolean functions on n variables, $r\leq b(n)=\lceil\log_2(n+1)\rceil$. We call a circuit using b(n) NEGATION gates negation-limited. We continue recent investigations into negation-limited circuit complexity, giving both upper and lower bounds.A circuit with inputs x1,..., xn and outputs $\neg x_1, \ldots, \neg x_n$ is called an inverter, for which $r=\lceil\log_2(n+1)\rceil$. Fischer has constructed negation-limited inverters of size O(n2 log n) and depth O(log n). Recently, Tanaka and Nishino have reduced the circuit size to O(n log2 n) at the expense of increasing the depth to log2 n. We construct negation-limited inverters of size O(n log n), with depth only O(log n), and we conjecture that this is optimal. We also improve a technique of Valiant for constructing monotone circuits for slice functions (introduced by Berkowitz).Next, we introduce some lower bound techniques for negation-limited circuits. We provide a 5n+3 log(n+1)-c lower bound for the size of a negation-limited inverter. In addition, we show that for two different restricted classes of circuit, negation-limited inverters require superlinear size.