The complexity of finite functions
Handbook of theoretical computer science (vol. A)
Negation-limited circuit complexity of symmetric functions
Information Processing Letters
On the Complexity of Negation-Limited Boolean Networks
SIAM Journal on Computing
On the Inversion Complexity of a System of Functions
Journal of the ACM (JACM)
Higher lower bounds on monotone size
STOC '00 Proceedings of the thirty-second annual ACM symposium on Theory of computing
Explicit lower bound of 4.5n - o(n) for boolena circuits
STOC '01 Proceedings of the thirty-third annual ACM symposium on Theory of computing
On the negation-limited circuit complexity of merging
Discrete Applied Mathematics - Special issue: Special issue devoted to the fifth annual international computing and combinatories conference (COCOON'99) Tokyo, Japan 26-28 July 1999
An Explicit Lower Bound of 5n - o(n) for Boolean Circuits
MFCS '02 Proceedings of the 27th International Symposium on Mathematical Foundations of Computer Science
On the negation-limited circuit complexity of sorting and inverting k-tonic sequences
COCOON'06 Proceedings of the 12th annual international conference on Computing and Combinatorics
Reductions for monotone Boolean circuits
Theoretical Computer Science
Linear-size log-depth negation-limited inverter for k-tonic binary sequences
Theoretical Computer Science
Linear-size log-depth negation-limited inverter for k-tonic binary sequences
TAMC'07 Proceedings of the 4th international conference on Theory and applications of models of computation
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We give improved lower bounds for the size of negation-limited circuits computing Parity and for the size of negation-limited inverters. An inverter is a circuit with inputs x1,...,xn and outputs ¬x1,...,¬xn. We show that (1) For n=2r–1, circuits computing Parity with r–1 NOT gates have size at least 6n–log2(n+1)–O(1) and (2) For n=2r–1, inverters with r NOT gates have size at least 8n–log2(n+1)–O(1). We derive our bounds above by considering the minimum size of a circuit with at most r NOT gates that computes Parity for sorted inputs x1≥⋯≥xn. For an arbitraryr, we completely determine the minimum size. For odd n, it is 2n–r–2 for ⌈log2(n+1)⌉–1≤r ≤n/2, and it is $\lfloor 3/2 \: n\rfloor-1$ for r ≥n/2. We also determine the minimum size of an inverter for sorted inputs with at most r NOT gates. It is 4n–3r for ⌈log2(n+1) ⌉≤r ≤n. In particular, the negation-limited inverter for sorted inputs due to Fischer, which is a core component in all the known constructions of negation-limited inverters, is shown to have the minimum possible size. Our fairly simple lower bound proofs use gate elimination arguments.