Reduced-instruction set multi-microcomputer system

Authors:
Lewis Foti;David English;Richard P. Hopkins;David J. Kinniment;Philip C. Treleaven;Wang Long Wang
Affiliations:
University of Newcastle upon Tyne, Newcastle upon Tyne, England;University of Newcastle upon Tyne, Newcastle upon Tyne, England;University of Newcastle upon Tyne, Newcastle upon Tyne, England;University of Newcastle upon Tyne, Newcastle upon Tyne, England;University of Newcastle upon Tyne, Newcastle upon Tyne, England;University of Newcastle upon Tyne, Newcastle upon Tyne, England
Venue:
AFIPS '84 Proceedings of the July 9-12, 1984, national computer conference and exposition
Year:
1984

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Abstract

This paper presents the initial design and implementation of a simple microcomputer with a reduced instruction set, which forms a building block for a parallel multi-microcomputer system. The microcomputer has a 16-bit word size, with each register and data element being 16 bits. It has less than 20 operators. Each microcomputer in the multi-microcomputer system is addressable, and behaves as a combined memory cell and processor that is able to service the LOAD, STORE, and EXECUTE operations. The multi-microcomputer system centers on a 16-bit global address space. An address consists of two parts: the high eight bits define a specific microcomputer, and the low eight bits define a word in that microcomputer. When the top eight bits are zero the address is considered local to the microcomputer. Although a microcomputer can load or store any word in the global address space, an attempt to execute code at an alien address causes execution to transfer to the specified microcomputer. Although the microcomputer design is based on 16-bit units, we ultimately wish to design the simplest microcomputer that is able to handle variable length information.