Formal verification of practical MPI programs

  • Authors:

  • Anh Vo;Sarvani Vakkalanka;Michael DeLisi;Ganesh Gopalakrishnan;Robert M. Kirby;Rajeev Thakur

  • Affiliations:

  • University of Utah, Salt Lake City, UT, USA;University of Utah, Salt Lake City, UT, USA;University of Utah, Salt Lake City, UT, USA;University of Utah, Salt Lake City, UT, USA;University of Utah, Salt Lake City, UT, USA;Argonne National Laboratory, Lemont, IL, USA

  • Venue:
  • Proceedings of the 14th ACM SIGPLAN symposium on Principles and practice of parallel programming
  • Year:
  • 2009

Quantified Score

Hi-index 0.02

Visualization

Abstract

This paper considers the problem of formal verification of MPI programs operating under a fixed test harness for safety properties without building verification models. In our approach, we directly model-check the MPI/C source code, executing its interleavings with the help of a verification scheduler. Unfortunately, the total feasible number of interleavings is exponential, and impractical to examine even for our modest goals. Our earlier publications formalized and implemented a partial order reduction approach that avoided exploring equivalent interleavings, and presented a verification tool called ISP. This paper presents algorithmic and engineering innovations to ISP, including the use of OpenMP parallelization, that now enables it to handle practical MPI programs, including:(i)~ParMETIS - a widely used hypergraph partitioner, and (ii)~MADRE - a Memory Aware Data Re-distribution Engine, both developed outside our group. Over these benchmarks, ISP has automatically verified up to 14K lines of MPI/C code, producing error traces of deadlocks and assertion violations within seconds.