Combined BEM/FEM substrate resistance modeling
Proceedings of the 39th annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Substrate optimization based on semi-analytical techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient techniques for accurate modeling and simulation of substrate coupling in mixed-signal IC's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A methodology is proposed to efficiently estimate the substrate noise generated by large scale aggressor circuits. Small spatial voltage differences within the ground distribution network of an aggressor circuit are exploited to reduce the overall number of input ports before the substrate extraction process. Specifically, the substrate of an aggressor circuit is partitioned into voltage domains where each domain is represented by a single substrate contact. The remaining ports of the substrate within that domain are ignored to reduce the computational complexity. A linear time algorithm is developed to identify these voltage domains and generate an equivalent contact. A reduction of more than four orders of magnitude in the number of extracted substrate resistances is demonstrated while introducing 20% error in the peak-to-peak value of the substrate noise voltage.