New efficient FFT algorithm and pipeline implementation results for OFDM/DMT applications
IEEE Transactions on Consumer Electronics
IEEE Communications Magazine
Automatic IP generation of FFT/IFFT processors with word-length optimization for MIMO-OFDM systems
EURASIP Journal on Advances in Signal Processing - Special issue on quantization of VLSI digital signal processing systems
Designing Fast Fourier Transform Accelerators for Orthogonal Frequency-Division Multiplexing Systems
Journal of Signal Processing Systems
MDC FFT/IFFT processor with variable length for MIMO-OFDM systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A pipelined Fast Fourier Transform and its inverse (FFT/IFFT) processor, which utilizes hardware resources efficiently, is proposed for MIMO-OFDM WLAN 802.11n. Compared with a conventional MIMO-OFDM implementation, (in which as many FFT/IFFT processors as the number of transmit/receive antennas is used), the proposed architecture (using hardware sharing among multiple data sequences) reduces hardware complexity without sacrificing system throughput. Further, the proposed architecture can support 1---4 input data sequences with sequence lengths of 64 or 128, as needed. The FFT/IFFT processor is synthesized using TSMC 0.18 um CMOS technology and saves 25% area compared to a conventional implementation approach using radix-23 algorithm. The proposed FFT/IFFT processor can be configured to improve power efficiency according to the number of input data sequences and the sequence length. The processor consumes 38 mW at 75 MHz for one input sequence with 64-point length; it consumes 87 mW at 75 MHz for four input sequences with length 128-point and can be efficiently used for IEEE 802.11n WLAN standard.