Discrete-time signal processing (2nd ed.)
Discrete-time signal processing (2nd ed.)
A New Approach to Pipeline FFT Processor
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
Stride Permutation Networks for Array Processors
ASAP '04 Proceedings of the Application-Specific Systems, Architectures and Processors, 15th IEEE International Conference
Permuting streaming data using RAMs
Journal of the ACM (JACM)
An Area Efficient FFT/IFFT Processor for MIMO-OFDM WLAN 802.11n
Journal of Signal Processing Systems
Radix rkFFTs: matricial representation and SDC/SDF pipeline implementation
IEEE Transactions on Signal Processing
A 2.4-GS/s FFT processor for OFDM-based WPAN applications
IEEE Transactions on Circuits and Systems II: Express Briefs
New efficient FFT algorithm and pipeline implementation results for OFDM/DMT applications
IEEE Transactions on Consumer Electronics
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents an multipath delay commutator (MDC)-based architecture and memory scheduling to implement fast Fourier transform (FFT) processors for multiple input multiple output-orthogonal frequency division multiplexing (MIMO-OFDM) systems with variable length. Based on the MDC architecture, we propose to use radix-Ns butterflies at each stage, where Ns is the number of data streams, so that there is only one butterfly needed in each stage. Consequently, a 100% utilization rate in computational elements is achieved. Moreover, thanks to the simple control mechanism of the MDC, we propose simple memory scheduling methods for input data and output bit/set-reversing, which again results in a full utilization rate in memory usage. Since the memory requirements usually dominate the die area of FFT/inverse fast Fourier transform (IFFT) processors, the proposed scheme can effectively reduce the memory size and thus the die area as well. Furthermore, to apply the proposed scheme in practical applications, we let Ns = 4 and implement a 4-stream FFT/IFFT processor with variable length including 2048, 1024, 512, and 128 for MIMO-OFDM systems. This processor can be used in IEEE 802.16 WiMAX and 3GPP long term evolution applications. The processor was implemented with an UMC 90-nm CMOS technology with a core area of 3.1 mm2. The power consumption at 40 MHz was 63.72/62.92/57.51/51.69 mW for 2048/1024/512/128-FFT, respectively in the post-layout simulation. Finally, we analyze the complexity and performance of the implemented processor and compare it with other processors. The results show advantages of the proposed scheme in terms of area and power consumption.