BURG: fast optimal instruction selection and tree parsing
ACM SIGPLAN Notices
Engineering a simple, efficient code-generator generator
ACM Letters on Programming Languages and Systems (LOPLAS)
Advanced compiler design and implementation
Advanced compiler design and implementation
The Jalapeño dynamic optimizing compiler for Java
JAVA '99 Proceedings of the ACM 1999 conference on Java Grande
Constraint driven code selection for fixed-point DSPs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Code selection for media processors with SIMD instructions
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Compilation techniques for multimedia processors
International Journal of Parallel Programming - Special issue on instruction-level parallelism and parallelizing compilation, Part 1
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Automatic intra-register vectorization for the Intel architecture
International Journal of Parallel Programming
Loop Parallelisation for the Jikes RVM
PDCAT '05 Proceedings of the Sixth International Conference on Parallel and Distributed Computing Applications and Technologies
NPC'10 Proceedings of the 2010 IFIP international conference on Network and parallel computing
Speculatively vectorized bytecode
Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers
Improving performance through deep value profiling and specialization with code transformation
Computer Languages, Systems and Structures
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Modern processors incorporate SIMD instructions to improve the performance of multimedia applications. Vectorizing compilers are therefore sought to efficiently generate SIMD instructions. With the existence of different families of SIMD instruction sets, the task of compiler writers is more complex. Moreover virtual machines, such as JVMs, are currently widely used for increasing the portability of programs across different platforms; performing SIMDization on these virtual machines would further require 'fast' compilation. This paper selects an efficient retargetable compilation technique, based on tree-pattern matching, which generates efficient SIMD code on static compilers, and studies its utility on the Jikes RVM. The paper extends BURS system used in Jikes optimizing compiler accordingly, and adds new rules for manipulating subword data for the IA-32 architecture. Initial experimental results show an overall speedup at runtime despite dynamic compilation overheads.