One-layer routing without component constraints
Journal of Computer and System Sciences
Generalized river routing - algorithms and performance bounds
Proc. of the Aegean workshop on computing on VLSI algorithms and architectures
The benefits of external wires in single row routing
Information Processing Letters
Near-optimal n-layer channel routing
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Journal of the ACM (JACM)
Three-Dimensional VLSI: a case study
Journal of the ACM (JACM)
Introduction to VLSI Systems
The impact of wire topology on channel routing
The impact of wire topology on channel routing
Computational Aspects of VLSI
The benefits of external wires in single row routing
Information Processing Letters
| Hi-index | 14.99 |
Much of the recent work on the automated design of VLSI chips has concentrated on routing problems associated with such designs. One major class of routing problems focuses on single-row routing. Recently, the traditional single-row routing model has been generalized to allow external wires. Under this generalized model, it is possible to route many more single-row routing instances than in the traditional model. There is, however, a clear disadvantage in the use of external wires, since they force a lengthening of the channels surrounding the single row of terminals. Thus, it is desirable for these generalized single-row routings to use a minimum number of external wires. A linear-time algorithm for determining the minimum number of external wires needed to route a given instance of single-row routing is provided here.