Systematic Unidirectional Error-Detecting Codes
IEEE Transactions on Computers
Dynamic base register caching: a technique for reducing address bus width
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
An analysis of the information content of address reference streams
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Workload and implementation considerations for dynamic base register caching
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Address compression through base register caching
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
Sequence-switch coding for low-power data transmission
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We develop a coding scheme that reduces switching transients by limiting the number of lines that simultaneously switch during transmission of address and data information over the I/O pins of a VLSI chip, or the lines of a system bus. The maximum number of lines that simultaneously switch can be reduced by a factor of two using simple and fast circuitry for encoding and decoding.