Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
Software Synthesis from Dataflow Graphs
Software Synthesis from Dataflow Graphs
Embedded Multiprocessors: Scheduling and Synchronization
Embedded Multiprocessors: Scheduling and Synchronization
Parameterized Looped Schedules for Compact Representationof Execution Sequences
ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
Proceedings of the conference on Design, automation and test in Europe
Functional DIF for Rapid Prototyping
RSP '08 Proceedings of the 2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping
A generalized scheduling approach for dynamic dataflow applications
Proceedings of the Conference on Design, Automation and Test in Europe
A mixed-mode vector-based dataflow approach for modeling and simulating LTE physical layer
Proceedings of the 47th Design Automation Conference
Port Based Actor Model with Kahn Process Network Model and Decidable Dataflow Model
Journal of Signal Processing Systems
A rule-based quasi-static scheduling approach for static islands in dynamic dataflow graphs
ACM Transactions on Embedded Computing Systems (TECS)
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For a number of years, dataflow concepts have provided designers of digital signal processing systems with environments capable of expressing high-level software architectures as well as low-level, performance-oriented kernels. To apply these proven techniques to new complex, dynamic applications, we identify repetitive sequences of atomic, repeatable actions ("modes") inside dynamic actors to expose more of the static nature of the application. In this work, we propose a mode grouping strategy that aids in the decomposition of a dynamic dataflow graph into a set of static dataflow graphs that interact dynamically. Mode grouping enables the discovery of larger static subgraphs improving scheduling results. We show that grouping modes results in improved schedules with lower memory requirements for implementations by up to 37% including a common imaging benchmark with dynamic behavior: 3D B-spline interpolation.