DARWIN: CMOS opamp synthesis by means of a genetic algorithm
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
GPCAD: a tool for CMOS op-amp synthesis
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Analysis and Design of Analog Integrated Circuits
Analysis and Design of Analog Integrated Circuits
CMOS Telecom Data Converters: Illustrated
CMOS Telecom Data Converters: Illustrated
Data Converters
Design of Two-Stage Miller-Compensated Amplifiers Based on an Optimized Settling Model
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
Linear passive networks with ideal switches: consistent initial conditions and state discontinuities
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2009 IEEE system-on-chip conference
Behavioral modeling of pipeline ADC building blocks
International Journal of Circuit Theory and Applications
Analog Integrated Circuits and Signal Processing
Hi-index | 0.00 |
We present modeling techniques for accurate estimation of settling errors in switched-capacitor (SC) circuits built with Miller-compensated operational transconductance amplifiers (OTAs). One distinctive feature of the proposal is the computation of the impact of signal levels (on both the model parameters and the model structure) as they change during transient evolution. This is achieved by using an event-driven behavioral approach that combines small- and large-signal behavioral descriptions and keeps track of the amplifier state after each clock phase. Also, SC circuits are modeled under closed-loop conditions to guarantee that the results remain close to those obtained by electrical simulation of the actual circuits. Based on these models, which can be regarded as intermediate between the more established small-signal approach and full-fledged simulations, design procedures for dimensioning SC building blocks are presented whose targets are system-level specifications (such as ENOB and SNDR) instead of OTA specifications. The proposed techniques allow to complete top-down model-based designs with 0.3-b accuracy.