A 1.2 V 10-bit 60-MS/s 23 mW CMOS pipeline ADC with 0.67 pJ/conversion-step and on-chip reference voltages generator

  • Authors:

  • Jesús Ruiz-Amaya;Manuel Delgado-Restituto;Ángel Rodríguez-Vázquez

  • Affiliations:

  • Institute of Microelectronics of Seville, IMSE-CNM-CSIC, University of Seville, Seville, Spain 41092;Institute of Microelectronics of Seville, IMSE-CNM-CSIC, University of Seville, Seville, Spain 41092;Institute of Microelectronics of Seville, IMSE-CNM-CSIC, University of Seville, Seville, Spain 41092

  • Venue:
  • Analog Integrated Circuits and Signal Processing
  • Year:
  • 2012

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Abstract

A 1.2 V 10-bit 60 MS/s pipeline Analog-to-Digital Converter (ADC), fabricated in a 130 nm CMOS technology, is presented. The prototype is composed by five 3-bit pipeline stages and a Sample and Hold (S&H) circuit at the front. Two-stage Miller-compensated Operational Transconductance Amplifiers (OTAs), offset-compensated comparators and bootstrapping sampling switches have been used due to the low voltage supply requirements. Special attention has been paid to the reduction of the power consumption using a thorough design methodology. The converter only consumes 23 mW including on-chip reference voltages and bias current generators. The differential and integral nonlinearity of the ADC are below 0.60 and 0.61 LSBs, respectively. The pipeline converter achieves an effective resolution above 9 bits along the Nyquist bandwidth, and obtains 0.67 pJ energy consumption per conversion, making it one of the most energy-efficient 10-bit video-rate pipeline ADC reported to date.