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ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
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IBM Journal of Research and Development
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
The impact of the nanoscale on computing systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Optimizing CMOS technology for maximum performance
IBM Journal of Research and Development - Advanced silicon technology
Large-scale deep unsupervised learning using graphics processors
ICML '09 Proceedings of the 26th Annual International Conference on Machine Learning
Location, location, location: the role of spatial locality in asymptotic energy minimization
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ACM Transactions on Architecture and Code Optimization (TACO)
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The scaling of CMOS technology has progressed rapidly for three decades, but may soon come to an end because of power-dissipation constraints. The primary problem is static power dissipation, which is caused by leakage currents arising from quantum tunneling and thermal excitations. The details of these effects, along with other scaling issues, are discussed in the context of their dependence on application. On the basis of these considerations, the limits of CMOS scaling are estimated for various application scenarios.