Explicit-Symbolic Modelling for Formal Verification

Authors:
Umberto Costa;Sérgio Campos;Newton Vieira;David Déharbe
Affiliations:
Departamento de Ciência da Computação, Universidade Federal de Minas Gerais, Belo Horizonte, Brazil;Departamento de Ciência da Computação, Universidade Federal de Minas Gerais, Belo Horizonte, Brazil;Departamento de Ciência da Computação, Universidade Federal de Minas Gerais, Belo Horizonte, Brazil;Departamento de Informática e Matemática Aplicada, Universidade Federal do Rio Grande do Norte, Natal, Brazil
Venue:
Electronic Notes in Theoretical Computer Science (ENTCS)
Year:
2005

Citing 10
Cited 0

Automatic verification of finite-state concurrent systems using temporal logic specifications

ACM Transactions on Programming Languages and Systems (TOPLAS)
Graph-Based Algorithms for Boolean Function Manipulation

IEEE Transactions on Computers
Formal methods: state of the art and future directions

ACM Computing Surveys (CSUR) - Special ACM 50th-anniversary issue: strategic directions in computing research
The Model Checker SPIN

IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
Model checking

Model checking
Automatic predicate abstraction of C programs

Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation
The SLAM project: debugging system software via static analysis

POPL '02 Proceedings of the 29th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Symbolic Model Checking

Symbolic Model Checking
Bebop: A Symbolic Model Checker for Boolean Programs

Proceedings of the 7th International SPIN Workshop on SPIN Model Checking and Software Verification
Combining Constraint Solving and Symbolic Model Checking for a Class of a Systems with Non-linear Constraints

CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification

Quantified Score

Hi-index	0.00

Visualization

Abstract

We propose a model that combines explicit and symbolic representations in an explicit-symbolic formal verification model. Both explicit and symbolic models have been successfully used in the verification of finite state concurrent systems, such as complex sequential circuits and communication protocols. The proposed model aims to use explicit and symbolic techniques simultaneously to verify the same model and to make it possible to employ the most efficient technique to each aspect of the model. First, we formalize the explicit-symbolic model and show how it can be generated from a labeled state-transition system. Then, we apply those ideas to systems described in the Verimag Intermediate Format and present the main algorithms for integrating the underlying models.