Fat-trees: universal networks for hardware-efficient supercomputing
IEEE Transactions on Computers
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SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
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IPPS '97 Proceedings of the 11th International Symposium on Parallel Processing
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Principles and Practices of Interconnection Networks
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Proceedings of the 33rd annual international symposium on Computer Architecture
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Exploring pattern-aware routing in generalized fat tree networks
Proceedings of the 23rd international conference on Supercomputing
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IBM Journal of Research and Development
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Euro-Par'05 Proceedings of the 11th international Euro-Par conference on Parallel Processing
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Proceedings of the 23rd international conference on Supercomputing
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Optical Switching and Networking
Euro-Par'13 Proceedings of the 19th international conference on Parallel Processing
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Interconnection networks based on the k-ary n-tree topology are widely used in high-performance parallel computers. However, this topology is expensive and complex to build. In this paper we evaluate an alternative tree-like topology that is cheaper in terms of cost and complexity because it uses fewer switches and links. This alternative topology leaves unused upward ports on switches, which can be rearranged to be used as downward ports. The increase of locality might be efficiently exploited by applications. We test the performance of these thin-trees, and compare it with that of regular trees. Evaluation is carried out using a collection of synthetic traffic patterns that emulate the behavior of scientific applications and functions within message passing libraries, not only in terms of sources and destinations of messages, but also considering the causal relationships among them. We also propose a methodology to perform cost and performance analysis of different networks. Our main conclusion is that, for the set of studied workloads, the performance drop in thin-trees is less noticeable than the cost savings.