Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Bounded Model Checking Using Satisfiability Solving
Formal Methods in System Design
Symbolic Model Checking
Automatic Symbolic Verification of Embedded Systems
IEEE Transactions on Software Engineering
Verification of Real Time Chemical Processing Systems
HART '97 Proceedings of the International Workshop on Hybrid and Real-Time Systems
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Counterexample-Guided Abstraction Refinement
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Hardware verification using ANSI-C programs as a reference
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Automatic verification of a turbogas control system with the murϕ verifier
HSCC'03 Proceedings of the 6th international conference on Hybrid systems: computation and control
Abstraction refinement for bounded model checking
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Efficient satisfiability modulo theories via delayed theory combination
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
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Many hybrid systems can be conveniently modeled as Piece-wise Affine Discrete Time Hybrid Systems PA-DTHS. As well known Bounded Model Checking (BMC) for such systems comes down to solve a Mixed Integer Linear Programming (MILP) feasibility problem. We present a SAT based BMC algorithm for automatic verification of PA-DTHSs. Using Counterexample Guided Abstraction Refinement (CEGAR) our algorithm gradually transforms a PA-DTHS verification problem into larger and larger SAT problems. Our experimental results show that our approach can handle PADTHSs that are more then 50 times larger than those that can be handled using a MILP solver.