An automated high-level topology generation procedure for continuous-time ΣΔ modulator

Authors:
Soumya Pandit;Chittaranjan Mandal;Amit Patra
Affiliations:
Institute of Radio Physics and Electronics, Kolkata, India;Indian Institute of Technology, Kharagpur, India;Indian Institute of Technology, Kharagpur, India
Venue:
Integration, the VLSI Journal
Year:
2010

Citing 11
Cited 1

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Abstract

This paper presents an automated procedure for generation of high-level topologies for continuous-time @S@D modulator system. A functional topology of the system is generated from the given transfer function model of the modulator. Mathematical transformation technique is applied iteratively over the initial topology to generate a functional topology which is optimized for modulator sensitivity, hardware complexity and relative power consumption. This is then implemented using behavioral models of operational transconductance amplifiers and capacitors. The generated high-level topology is ensured to work with reasonable accuracy under non-ideal conditions. The entire procedure has been implemented in Matlab/Simulink environment. Numerical results have been provided to demonstrate the procedure.