Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
Multiprocessor scheduling to account for interprocessor communication
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IEEE Transactions on Parallel and Distributed Systems
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IEEE Transactions on Parallel and Distributed Systems
Throughput Analysis of Synchronous Data Flow Graphs
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IEEE Transactions on Parallel and Distributed Systems
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Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Multiprocessor resource allocation for throughput-constrained synchronous dataflow graphs
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The programming complexity of increasingly parallel processors calls for new tools to assist programmers in utilising the parallel hardware resources. In this paper we present a set of models that we have developed to form part of a tool which is intended for iteratively tuning the mapping of dataflow graphs onto manycores. One of the models is used for capturing the essentials of manycores that are identified as suitable for signal processing and which we use as target architectures. Another model is the intermediate representation in the form of a timed configuration graph, describing the mapping of a dataflow graph onto a machine model. Moreover, this IR can be used for performance evaluation using abstract interpretation. We demonstrate how the models can be configured and applied in order to map applications on the Raw processor. Furthermore, we report promising results on the accuracy of performance predictions produced by our tool. It is also demonstrated that the tool can be used to rank different mappings with respect to optimisation on throughput and end-to-end latency.