Optimization of regular expression pattern matching circuits on FPGA
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
A Scalable Architecture For High-Throughput Regular-Expression Pattern Matching
Proceedings of the 33rd annual international symposium on Computer Architecture
Fast and memory-efficient regular expression matching for deep packet inspection
Proceedings of the 2006 ACM/IEEE symposium on Architecture for networking and communications systems
The shunt: an FPGA-based accelerator for network intrusion prevention
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Supercharging planetlab: a high performance, multi-application, overlay network platform
Proceedings of the 2007 conference on Applications, technologies, architectures, and protocols for computer communications
DPICO: a high speed deep packet inspection engine using compact finite automata
Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems
Synthesis of regular expressions targeting FPGAs: current status and open issues
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
The NIDS cluster: scalable, stateful network intrusion detection on commodity hardware
RAID'07 Proceedings of the 10th international conference on Recent advances in intrusion detection
NetFPGA—An Open Platform for Teaching How to Build Gigabit-Rate Network Switches and Routers
IEEE Transactions on Education
Improving IPS by network processors
The Journal of Supercomputing
Hi-index | 0.00 |
Intrusion detection remains an important and challenging task in current and next generation networks (NGN). Emerging technologies such as multi-core processors and virtualization have changed the architecture of the building elements of NGN significantly, thus call for rethinking of how network processing is done. In this paper, we propose distributed intrusion detection using intelligent network interfaces where additional processing capabilities are available. We design and implement a prototype to perform pattern matching using network processors since pattern matching is one of the important workloads in intrusion detection. Through the experimental results, we show the feasibility and performance of distributed intrusion detection in next generation networks.