Cache performance analysis of traversals and random accesses
Proceedings of the tenth annual ACM-SIAM symposium on Discrete algorithms
Piranha: a scalable architecture based on single-chip multiprocessing
Proceedings of the 27th annual international symposium on Computer architecture
Introduction to Algorithms
Hybrid multi-core architecture for boosting single-threaded performance
ACM SIGARCH Computer Architecture News
A Flexible Heterogeneous Multi-Core Architecture
PACT '07 Proceedings of the 16th International Conference on Parallel Architecture and Compilation Techniques
Multi-core architectures and streaming applications
Proceedings of the 2008 international workshop on System level interconnect prediction
Efficient operating system scheduling for performance-asymmetric multi-core architectures
Proceedings of the 2007 ACM/IEEE conference on Supercomputing
Multicore is bad news for supercomputers
IEEE Spectrum
| Hi-index | 0.00 |
After the successful implementation of the dual and quad core processors, the designers are now thinking to place hundreds or even thousand of cores on a single chip. But this practice may lead to many basic and fundamental restrictions like interconnection of cores, memory size and its access patterns, cache design, number of cache levels etc. To overcome the cache related problems for many core processors two new multi-level cache models, LogN and LogN+1, have been proposed. These models are based on binary tree data structure. In this paper two design approaches for defining multi-level cache hierarchy for these two models are discussed. These two approaches are based on use of arithmetic and geometric propagation. After analyzing both these approaches for both LogN and LogN+1 model, the geometric propagation approach found much better for defining cache hierarchy in terms of size, frequency and cost. Also, cache access time for a core in a cache hierarchy designed using geometric propagation found much lesser than a cache hierarchy designed using arithmetic propagation.