Introduction to finite fields and their applications
Introduction to finite fields and their applications
IEEE Transactions on Computers
VLSI Designs for Multiplication over Finite Fields GF (2m)
AAECC-6 Proceedings of the 6th International Conference, on Applied Algebra, Algebraic Algorithms and Error-Correcting Codes
O(log(n)) Parallel Time Finite Field Inversion
AWOC '88 Proceedings of the 3rd Aegean Workshop on Computing: VLSI Algorithms and Architectures
Network coding: an instant primer
ACM SIGCOMM Computer Communication Review
XORs in the air: practical wireless network coding
Proceedings of the 2006 conference on Applications, technologies, architectures, and protocols for computer communications
Systolic Multipliers for Finite Fields GF(2m)
IEEE Transactions on Computers
A Cellular-Array Multiplier for GF(2m)
IEEE Transactions on Computers
Peer-to-Peer File Sharing Based on Network Coding
ICDCS '08 Proceedings of the 2008 The 28th International Conference on Distributed Computing Systems
A distributed bandwidth partitioning scheme for concurrent network-coded multicast sessions
GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
IEEE Transactions on Information Theory
A Random Linear Network Coding Approach to Multicast
IEEE Transactions on Information Theory
Design and evaluation of random linear network coding Accelerators on FPGAs
ACM Transactions on Embedded Computing Systems (TECS)
Hi-index | 0.00 |
This paper presents and analyzes novel hardware designs for high-speed network coding. Our designs provide efficient methods to perform Galois field (GF) dot products and matrix inversions, which are important operations in network coding. Encoder designs that perform GF dot products and vary with respect to the number of messages combined, Galois field size, and input message size are implemented and analyzed to evaluate design tradeoffs. We investigate single cycle, multicycle, and pipelined designs with and without feedback mechanisms for encoding multiple sets of messages. The decoder is implemented as a multi-cycle design and performs GF matrix inversion followed by multiple GF dot products. Our designs are synthesized with a 65nm standard cell library and compared in terms of area, critical path delay, and throughput. Designs combining four messages achieve throughputs of more than 30 Gbps. Our designs can scale to achieve much higher throughput through the use of additional hardware.