Energy efficient hardware architecture of LU triangularization for MIMO receiver

Authors:
Ji-Woong Choi;Jungwon Lee;Byung Gueon Min;Jongsun Park
Affiliations:
Marvell Semiconductor, Santa Clara, CA;Marvell Semiconductor, Santa Clara, CA;Mewtel Technology, Seoul, Korea;School of Electrical Engineering, Korea University, Seoul, Korea
Venue:
IEEE Transactions on Circuits and Systems II: Express Briefs
Year:
2010

Citing 6
Cited 0

Accuracy and Stability of Numerical Algorithms

Accuracy and Stability of Numerical Algorithms
Introduction to Algorithms

Introduction to Algorithms
Ultra Low Power CORDIC Processor for Wireless Communication Algorithms

Journal of VLSI Signal Processing Systems
An Improved Systolic Architecture for LU Decomposition

ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR Decomposition

VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Introduction to Space-Time Wireless Communications

Introduction to Space-Time Wireless Communications

Quantified Score

Hi-index	0.00

Visualization

Abstract

An energy-efficient hardware architecture of complex-valued matrix lower-upper (LV) triangularization for multi-input-multi-output (MIMO) receivers is presented in this paper. In the LV triangularization process, Gaussian elimination operation is expressed as a series of vector-scalar products, where basic common computations can be precomputed and shared to reduce computational complexity. Our computation-sharing-based architecture was implemented using a 0.25-µm CMOS process, and the hardware can perform LV triangularization from 2 × 2 to 8 × 8 matrices. Numerical results show that the proposed architecture has considerable energy savings over conventional matrix triangularization schemes.