Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Introduction to Formal Hardware Verification: Methods and Tools for Designing Correct Circuits and Systems
Symbolic Model Checking
Hardware Design and Petri Nets
Hardware Design and Petri Nets
Direct synthesis of timed circuits from free-choice STGs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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System verification plays an important role in large scale and complex systems. However, it is very difficult for designers other than the specialist who is well versed in Temporal Logic to specify behaviors of the system. This article considers the case where designers of systems can specify temporal formulas easily in system verification. We propose a method by which temporal formulas can be obtained inductively for specifications in system verification. System designers can easily derive complex temporal formulas by using the specification method.