Optimal power reduction based on DVFS algorithm for video decoders

Authors:
Seungho Jeong;Heejune Ahn
Affiliations:
SeoulTech (Seoul National University of Science and Technology), Nowon-gu, Seoul, Republic of Korea;SeoulTech (Seoul National University of Science and Technology), Nowon-gu, Seoul, Republic of Korea
Venue:
Proceedings of the 2011 ACM Symposium on Research in Applied Computation
Year:
2011

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Abstract

This paper proposes an optimal DVFS (Dynamic Voltage and Frequency Scaling) scheduling algorithm for decoders. Many DVFS techniques for video decoders have been proposed as a system level power-reduction technique. In this paper, based on the similarity in the system model with the 'Maximal Traffic Smoothing Algorithm [1],' an optimal scheduling algorithm and its schedulable conditions are presented. The simulation results show the optimal algorithm outperforms the previous heuristic algorithms by 7% on average. Furthermore, the performance gain saturates at about 10 frame size of the display buffers, i.e. the GOP level.