Watermarking techniques for intellectual property protection
DAC '98 Proceedings of the 35th annual Design Automation Conference
Signature hiding techniques for FPGA intellectual property protection
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Robust FPGA intellectual property protection through multiple small watermarks
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Robust techniques for watermarking sequential circuit designs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Information Hiding Terminology - Results of an Informal Plenary Meeting and Additional Proposals
Proceedings of the First International Workshop on Information Hiding
Hiding Signatures in Graph Coloring Solutions
IH '99 Proceedings of the Third International Workshop on Information Hiding
Zero Knowledge Watermark Detection
IH '99 Proceedings of the Third International Workshop on Information Hiding
Proving Ownership of Digital Content
IH '99 Proceedings of the Third International Workshop on Information Hiding
Keyless Public Watermarking for Intellectual Property Authentication
IHW '01 Proceedings of the 4th International Workshop on Information Hiding
Generic ILP versus specialized 0-1 ILP: an update
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Fast public-key watermarking of compressed video
ICIP '97 Proceedings of the 1997 International Conference on Image Processing (ICIP '97) 3-Volume Set-Volume 1 - Volume 1
N-variant IC design: methodology and applications
Proceedings of the 45th annual Design Automation Conference
Active control and digital rights management of integrated circuit IP cores
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Integrated circuits metering for piracy protection and digital rights management: an overview
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
An efficient locking and unlocking method of sequential systems
Proceedings of the 2012 ACM Research in Applied Computation Symposium
The undetectable and unprovable hardware trojan horse
Proceedings of the 50th Annual Design Automation Conference
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In this paper, we consider how to hide information into finite state machine (FSM), one of the popular computation models. The key advantage of hiding information in FSM is that the hidden information becomes inexpensive to retrieve, yet still hard to remove or delete. This is due to the fact that verifying certain FSM properties is easy, but changing them requires efforts equivalent to redoing all the design and implementation stages after FSM synthesis. We first observe that not all the FSM specifications (or transitions) are needed during the state minimization phase. We then develop a Boolean Satisfiability (SAT) based algorithm to discover, for a given minimized FSM, a maximal set of redundant specifications. Manipulating such redundancy enables us to hide information into the FSM without changing the given minimized FSM. Moreover, when the original FSM does not possess sufficient redundancy to accommodate the information to be embedded, we propose a state duplication technique to introduce additional redundancy. We analyze these methods in terms of correctness, capacity of hiding data, overhead, and robustness against possible attacks. We take sequential circuit design benchmarks, which adopt the FSM model, as the simulation testbed to demonstrate the strength of the proposed information hiding techniques.